A common method of examining microscopic (including nanometer scale) structures for process monitoring and failure analysis is to cut a trench in the structure with a focused ion beam (FIB) to expose a cross section orthogonal to the surface, and then view the cross section with a scanning electron microscope (SEM). Another technique is to extract a thin sample from the structure to view on a transmission electron microscope (TEM). Ion beam milling artifacts, however, can distort the exposed structure so that the electron beam image does not accurately represent the original structure.
One type of artifact is referred to as “curtaining,” because it can look like a curtain. Curtaining occurs when different materials are removed at different rates, such as when the sample is composed of materials that are milled at different rates by the ion beam. Unfilled holes can cause curtaining, as can the milling by the “tails” of the Gaussian shaped ion beam. Curtaining can also occur when milling a surface that has an irregular shape. Sometimes a protective layer is deposited on top of the region of interest to reduce curtaining from the milling caused by the tail of the Gaussian-shaped beam as described, for example, in U.S. Pat. Pub. No. 20130143412 for “Methods for Preparing Thin Samples for Tem Imaging” and U.S. Pat. Pub. No. 20120199923 for “Method and Apparatus for Controlling Topographical Variation on a Milled Cross-Section of a Structure,” both of which are assigned to the assignee of the present invention.
Severe artifacts can be created when exposing a feature having a height that is much greater than its width. Such a structure is referred to as a “high aspect ratio” feature. For example, a feature having a height four times greater than its width would be considered a high aspect ratio feature. Holes or contacts between layers in an integrated circuit are often high aspect ratio structures, having heights that are several times greater than their widths.
As semiconductor fabrication processes pack more circuitry into smaller packages, integrated circuit designs are becoming more three-dimensional (3D) and incorporate more high aspect ratio features. In analyzing high aspect ratio structures, especially unfilled contact holes, for the 3D integrated circuit (IC) structures such as 3D NAND circuits, conventional ion beam sample preparation causes unacceptable artifacts, such as distortion and curtaining.
When there are unfilled high aspect ratio holes on a sample, there are large differences in the milling rates between the solid regions and the regions adjacent to the unfilled hole. The large difference in milling rates results in curtaining or waterfall effects, another artifact that distorts the shape of the hole. Structure damage and artifacts from the ion beam milling process make it difficult to analyze high aspect ratio vertical structures.
One structural feature that process engineers need to observe is a through-silicon via (TSV). Cross-sectioning TSVs is a common practice in semiconductor labs to characterize voids and surface interfaces. Due to the depth of TSVs, typically 50-300 nm, milling a cross section of a TSV with an ion beam can result in substantial curtaining.
Because of the damage and artifacts caused by the use of ion beam milling to expose features, the images do not faithfully show the results of the fabrication process. The artifacts interfere with measurements and with an assessment of the fabrication process because the image and measurements show the effects of the sample preparation, as well as the result of the original fabrication process.
High aspect ratio holes or trenches with complex material stacks are also difficult to measure with other known methods, such as scatterometry and critical dimension scanning electron microscopy (CD-SEM).
What is needed is a way to expose regions of interest for examination and/or measurement and produce an accurate image that reflects the fabrication process without damaging the regions of interest or creating artifacts in the exposed surface.